Archive | December, 2013

Understanding Boot Time Variability with the Zynq ZC702

One of the challenges of boot time reduction is understanding why the boot time of a device may vary with each reboot, this is important because we strive not only for minimal boot times but for consistently minimal boot times. This post uses a Xilinx Zynq platform to demonstrate how we can measure, understand and find the causes of boot time variability. We’ll also provide an insight into how we use automation at Embedded Bits to improve the process.

To explore boot time variability we’ll be using Xilinx’s Zynq-7000 based ZC702 evaluation kit. The Zynq range of SoC’s cleverly combine a dual-core Cortex A9 MPCore with programmable logic (Artix-7 FPGA). The ZC702 is provided with a ‘Base Targeted Reference Design (TRD)‘ (a Linux distribution on an SD card) – we’ll use this to perform our investigation against.

By its very nature, the only way to measure variability is to measure the boot time over and over again during successive runs (time consuming!). At Embedded Bits where possible we install development boards into our board farm – along with providing benefits such as board sharing and collaborative working, it crucially provides automation – we’ll take advantage of this as we explore boot time variability. We’ll start by instructing the farm to repeatedly reboot the board whilst capturing boot logs.

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